View TB62209F_71616.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TB62209F
Preliminary
TOSHIBA BiCD Processor IC Silicon Monolithic
TB62209F
Stepping Motor Driver IC Using PWM Chopper Type
The TB62209F is a stepping motor driver driven by chopper micro-step pseudo sine wave. The TB62209F integrates a decoder for CLK input in micro steps as a system to facilitate driving a two-phase stepping motor using micro-step pseudo sine waves. Micro-step pseudo sine waves are optimal for driving stepping motors with low-torque ripples and at low oscillation. Thus, the TB62209F can easily drive stepping motors with low-torque ripples and at high efficiency. Also, TB62209F consists output steps by DMOS (Power MOS Weight: g (typ.) FET), and that makes possible to control the output power dissipation much lower than ordinary IC with bipolar transistor output. The IC supports Mixed Decay mode for switching the attenuation ratio at chopping. The switching time for the attenuation ratio can be switched in four stages according to the load.
Features
* * * * * * * * * * * * Bipolar stepping motor can be controlled by a single driver IC Monolithic BiCD IC Low ON-resistance of Ron = 0.5 (Tj = 25C @1.0 A: typ.) Built-in decoder and 4-bit DA converters for micro steps Built-in ISD, TSD, VDD &VM power monitor (reset) circuit for protection Built-in charge pump circuit (two external capacitors) 36-pin power flat package (HSOP36-P-450-0.65) Output voltage: 40 V max Output current: 1.8 A/phase max 2-phase, 1-2 (type 2) phase, W1-2 phase, 2W1-2 phase, 4W1-2 phase, or motor lock mode can be selected. Built-in Mixed Decay mode enables specification of four-stage attenuation ratio. Chopping frequency can be set by external resistors and capacitors. High-speed chopping possible at 100 kHz or higher.
Note: When using the IC, pay attention to thermal conditions. These devices are easy damage by high static voltage. In regards to this, please handle with care.
1
2001-09-05
TB62209F
Block Diagram
1. Overview
TORQUE 1 TORQUE 2 MDT 1 MDT 2
RESET CW/CCW ENABLE STANDBY D MODE 3 D MODE 2 D MODE 1 CLK OCS Micro-step decorder VDD MO
Chopper OSC CR
Current Level Set Vref Torque control 4-bit DA (sine angle control)
CR-CLK converter
Current Feedback (x2) RS VRS 1 RS COMP 1 Output control (Mixed Decay control)
VM VM
VRS 2
RS COMP 2
Ccp C Charge Pump Unit
STANDBY Output (H-bridge) x2 ENABLE VM
ISD
TSD
Ccp B Ccp A
VDDR/VMR protect Protection Unit
VDD
TSD protect
Stepping Moter
2
2001-09-05
TB62209F
2. LOGIC UNIT A/B (C/D unit is the same as A/B unit)
Function This circuit is used to input from the DATA pins micro-step current setting data and to transfer them to the subsequent stage. By switching the SETUP pin, the data in the mixed decay timing table can be overwritten.
MDT 1 MDT 2 TORQUE 1 TORQUE 2 DATA MODE
D MODE 1 D MODE 2 D MODE 3 CW/CCW CLK STANDBY RESET
Micro-step decoder
Decay x 2 bits A unit side
Micro-step current data x 4 bits A unit side Phase x 1 bit A unit side
ENABLE Output control circuit
Torque x 2 bits
Decay x 2 bits B unit side
Micro-step current data x 4 bits B unit side
Phase x 1 bit B unit side
Current feedback circuit
Mixed Decay circuit
DA circuit
Output control circuit
3
2001-09-05
TB62209F
3. Current feedback circuit and current setting circuit
Function The current setting circuit is used to set the reference voltage of the output current using the current setting decoder. The current feedback circuit is used to output to the output control circuit the relation between the set current value and output current. This is done by comparing the reference voltage output to the current setting circuit with the potential difference generated when current flows through the current sense resistor connected between RS and VM. The chopping waveform generator circuit to which CR is connected is used to generate clock used as reference for the chopping frequency.
TORQUE 0, 1 Decoder Unit CURRENT 0-3
Vref
100 85 70 50 Torque control circuit
15 Micro-step current 14 setting 13 12 selector 11 circuit 10 9 8 7 6 5 4 4-bit 3 DA 2 circuit 1 0
Chopping waveform generator circuit
CR
Waveform shaping circuit Chopping reference circuit
Mixed Decay timing circuit
Current setting circuit DA circuit
Output stop signal (ALL OFF)
RS
VRS circuit 1 (detects potential difference between RS and VM)
RS COMP circuit 1 (Note 1) Output control circuit
NF (set current reached signal)
VM
VRS circuit 2 (detects potential difference between VM and RS) Current feedback circuit
RS COMP circuit 2 (Note 2)
RNF (set current monitor signal)
Note 1: RS COMP1: Compares the set current with the output current and outputs a signal when the output current reaches the set current. Note 2: RS COMP2: Compares the set current with the output current at the end of Fast mode during chopping. Outputs a signal when the set current is below the output current.
4
2001-09-05
TB62209F
4. Output control circuit, current feedback circuit and current setting circuit
Micro-step current setting decoder circuit
Chopping reference circuit
DECAY MODE Output control circuit PHASE
Mixed Decay timing circuit
Current feedback circuit
NF set current reached signal RNF set current monitor signal Output stop signal Mixed Decay timing Charge Start U1 U2 L1 L2
CR counter
CR Serector
Current setting circuit
Output circuit
Output RESET signal
STANDBY
VDD
VM Power supply for upper drive output
Output pin
ISD circuit
VM
VMR circuit
VDD
VDDR circuit
Internal stop signal select circuit
Charge pump halt signal Charge pump circuit
VH
Output circuit
Cop A
Cop B
Cop C TSD circuit VDDR: VDD power on Reset VMR: VM power on Reset ISD: Current shutdown circuit TSD: Thermal shutdown circuit Protection circuit Micro-step current setup latch clear signal LOGIC Mixed Decay timing table clear signal
Note: The STANDBY pins are pulled down in the IC by 10-k resistor. When not using the pin, connect it to GND. Otherwise, malfunction may occur.
5
2001-09-05
TB62209F
5. Output equivalent circuit (A/B unit (C/D unit is the same as A/B unit)
RS A Power supply for upper drive output (VH) From output control circuit U1 U2 L1 L2 Output driver circuit Phase A
To VM RRS A
U1
U2
Output A L1 L2 Output A
VM B
RSB Power supply for upper drive output (VH) From output control circuit U1 U2 L1 L2 Output driver circuit Phase B
RRS B
U1
U2
Output B L1 L2 Output B
M
PGND
Note: The diode on the dotted line is parasitic diode.
6
2001-09-05
TB62209F
6. Input equivalent circuit
1. Input circuit (CLK, TORQUE, MDT, CW/CCW, DATA MODE, Decay Mode)
VDD
IN 150 To Logic IC
VSS
GND
2.
Input circuit ( RESET , ENABLE, STANDBY)
VDD
IN 100 k 150 To Logic IC
VSS
GND
3.
Vref input circuit
VDD
IN
2 To DA circuit
VSS
GND
4.
Output circuit (MO, PROTECT)
VDD
OUT 150
VSS
GND
7
2001-09-05
TB62209F
Pin Assignment (top view)
D MODE 1 1 D MODE 2 2 D MODE 3 3 CW/CCW 4 VDD 5 Vref 6 NC 7 NC 8 RS B 9
36 CR 35 CLK 34 ENABLE 33 OUT B 32 RESET 31 DATA MODE 30 NC 29 OUT B 28 PGND
(FIN)
TB62209F
(FIN)
RS A 10 NC 11 NC 12 VM 13 STANDBY 14 Ccp A 15 Ccp B 16 Ccp C 17 MO 18
27 PGND 26 OUT A 25 NC 24 MDT 2 23 MDT 1 22 OUT A 21 TORQUE2 20 TORQUE1 19 PROTECT
Pin Assignment for PWM in Data Mode
D MODE 1 GA+ (OUT A, A ) D MODE 2 GA- (OUT A, A ) D MODE 3 GB+ (OUT B, B ) CW/CCW GB- (OUT B, B ) Note: Pin assignment above is different at data mode and PWM.
8
2001-09-05
TB62209F
Pin Description 1
Pin Number Symbol Function D MODE 3, 2, 1 = 1 D MODE 1 LLL: Same function as that of STANDBY pin LLH: Motor Lock mode LHL: 2-Phase Excitation mode 2 D MODE 2 Motor drive mode setting pin LHH: 1-2 Phase Excitation (A) mode HLL: 1-2 Phase Excitation (B) mode HLH: W1-2 Phase Excitation mode 3 D MODE 3 HHL: 2W1-2 Phase Excitation mode HHH: 4W1-2 Phase Excitation mode 4 5 6 7 8 9 CW/CCW VDD Vref NC NC RS B Sets motor rotation direction Logic power supply connecting pin Reference power supply pin for setting output current Not connected Not connected Unit-B power supply pin (connecting pin for power detection resistor) CW: Forward rotation CCW: Reverse rotation Connect to logic power supply (5 V). Connect to supply voltage for setting current. Not wired Not wired Connect current sensing resistor between this pin and VM. Connect to power ground. FIN FIN FIN Logic ground pin The pin functions as a heat sink. Design pattern taking heat into consideration. Connect current sensing resistor between this pin and VM. Not wired Not wired Remarks
10 11 12
RS A NC NC
Unit-A power supply pin (pin connecting power detection resistor) Not connected Not connected
Pin Assignment for PWM in Data Mode
D MODE 1 GA+ (OUT A, A ) D MODE 2 GA- (OUT A, A ) D MODE 3 GB+ (OUT B, B ) CW/CCW GB- (OUT B, B )
9
2001-09-05
TB62209F
Pin Description 2
Pin Number 13 VM
STANDBY
Symbol
Function Motor power supply monitor pin All-function-initializing and Low Power Dissipation mode pin Pin connecting capacitor for boosting output stage drive power supply (storage side connected to GND) Pin connecting capacitor for boosting output stage drive power supply (charging side)
Remarks Connect to motor power supply. H: Normal operation L: Operation halted Charge pump output halted Connect capacitor for charge pump (storage side) VM and VDD are generated. Connect capacitor for charge pump (charging side) between this pin and Ccp C. Connect capacitor for charge pump (charging side between this pin and Ccp B. Outputs High level in 4W1-2, 2W1-2, W1-2, or 1-2 Phase Excitation mode with electrical angle of 0 (phase B: 100%, phase A: 0%). In 2-Phase Excitation mode, outputs High level with electrical angle of 0 (phase B: 100%, phase A: 100%).
14
15
Ccp A
16 17
Ccp B Ccp C
18
MO
Electrical angle (0) monitor pin
19 20 21 22 23 24
PROTECT TORQUE 1
TSD operation detector pin
Detects thermal shut down (TSD) and outputs High level. Torque 2, 1 = HH: 100% LH: 85%
Motor torque switch setting pin TORQUE 2 OUT A MDT 2 Mixed Decay mode setting pins MDT 1 LH: 37.5% LL: 12.5% Channel A output pin HL: 70% LL: 50% MDT 2, 1 = HH: 100% HL: 75%
10
2001-09-05
TB62209F
Pin Description 3
Pin Number 25 26 27 FIN 28 29 30 NC OUT A PGND FIN PGND OUT B NC Symbol Not connected Channel A output pin Power ground pin Logic ground pin Power ground pin Channel B output pin Not connected Not wired H: Controls external PWM. L: CLK-IN mode 31 DATA MODE Clock input and PWM We recommend this pin normally be used as CLK-IN mode pin (Low). In PWM mode, functions such as constant current control do not operate. Forcibly initializes electrical angle. 32 RESET Initializes electrical angle. At this time we recommend ENABLE pin be set to Low to prevent misoperation. H: Resets electrical angle. L: Normal operation 33 34 OUT B ENABLE Channel B output pin Output enable pin Inputs CLK for determining number of motor rotations. Forcibly turns all output transistors off. Electrical angle is incremented by one for each CLK input. CLK is reflected at rising edge. 36 CR Chopping reference frequency reference pin (for Determines chopping frequency. setting chopping frequency) Function Not wired Connect all power ground pins and VSS to GND. The pin functions as a heat sink. Design pattern taking heat into consideration. Connect all power ground pins to GND. Remarks
35
CLK
11
2001-09-05
TB62209F
1. Function of CW/CCW
CW/CCW switches the direction of stepping motor rotation.
Input H L
Function Forward (CW) Reverse (CCW)
2. Function of MDT 1/MDT 2
MDT 1/MDT 2 specifies the current attenuation speed at constant current control. The larger the rate (%), the larger the attenuation of the current. Also, the peak current value (current ripple) becomes larger. (Typical value is 37.5%.)
MDT 2 L L H H
MDT 1 L H L H
Function 12.5% Mixed Decay mode 37.5% Mixed Decay mode 75% Mixed Decay mode 100% Mixed Decay mode (Fast Decay mode)
3. Function of TORQUE X
TORQUE X changes the current peak value in four steps. Used to change the value of the current used, for example, at startup and fixed-speed rotation.
TORQUE 2 H L H L
TORQUE 1 H H L L
Comparator Reference Voltage 100% 85% 70% 50%
4. Function of RESET (forced initialization of electrical angle)
With the CLK input method (decoder method), unless CLKs are counted, except MO, where the electrical angle is at that time is not known. Thus, this method is used to forcibly initialize the electrical angle. For example, used to change the excitation mode to another drive mode during output from MO (electrical angle = 0).
Input H L Function Initializes electrical angle to 0 Normal operation
12
2001-09-05
TB62209F
5. Function of ENABLE (output operation)
ENABLE forcibly turns OFF all output transistors at operation. Data such as electrical angle and operating mode are all retained.
Input H L
Function Operation enabled (active) Output halted (operation other than output active)
6. Function of STANDBY
STANDBY halts the charge pump circuit (power supply booster circuit) as well as halting output. We recommend setting to Standby mode at power on. (At this time, data on the electrical angle are retained.)
Input H
Function Operation enabled (active) Output halted (Low Power Dissipation mode) Charge pump halted
L
7. Functions of Excitation Modes
Excitation Mode 1 2 3 4 5 6 7 8 Low Power Dissipation mode Motor Lock mode 2-Phase Excitation mode 1-2 Phase Excitation (A) 1-2 Phase Excitation (B) W1-2 Phase Excitation 2W1-2 Phase Excitation 4W1-2 Phase Excitation DM3 0 0 0 0 1 1 1 1 DM2 0 0 1 1 0 0 1 1 DM1 0 1 0 1 0 1 0 1 Remarks Standby mode Charge pump halted Locks only at 0 electrical angle. 45 135 225 315 45 Low-torque, 1-bit micro-step change High-torque, 1-bit micro-step change 2-bit micro-step change 3-bit micro-step change 4-bit micro-step change
13
2001-09-05
TB62209F
8. Function of DATA MODE
DATA MODE switches external duty control (forced PWM control) and constant current CLK-IN control. In Phase mode, H-bridge can be forcibly inverted and output only can be turned off. Constant current drive including micro-step drive can only be controlled in CLK-IN mode.
Input H L
Function PHASE MODE CLK-IN MODE
Note 1: Normally, use CLK-IN mode.
9. Electrical Angle Setting immediately after Initialization
In Initialize mode (immediately after RESET is released), the following currents are set. In Low Power Dissipation mode, the internal decoder continues incrementing the electrical angle but current is not output. Note that the initial electrical angle value in 2-Phase Excitation mode differs from that in nW1-2 (n = 0, 1, 2, 4) Phase Excitation mode.
Excitation Mode 1 2 3 4 5 6 7 8 Low Power Dissipation mode Motor Lock mode 2-Phase Excitation 1-2 Phase Excitation (A) 1-2 Phase Excitation (B) W1-2 Phase Excitation 2W1-2 Phase Excitation 4W1-2 Phase Excitation
IB (%) 100 100 100 100 100 100 100 100
IA (%) 0 0 100 0 0 0 0 0
Remarks Electrical angle incremented but no current output Electrical angle incremented but no motor rotation due to no IA output 45 0 0 0 0 0
Note 2: Where, IB = 100% and IA = 0%, the electrical angle is 0. Where, IB = 0% and IA = 100%, the electrical angle is +90.
14
2001-09-05
TB62209F
10. Function of DATA MODE (Phase A mode used for explanation)
DATA MODE inputs the external PWM signal (duty signal) and controls the current. Functions such as constant current control and overcurrent protector do not operate. Use this mode only when control cannot be performed in CLK-IN mode.
GA+ (1) (2) (3) (4) L L H H
GA- L H L H Output off A+ phase: Low A+ phase: High Output off
Output State
A- phase: High A- phase: Low
(1) (4)
(2)
(3)
U1 OFF
U2 OFF
U1 OFF (Note)
U2 ON
U1 ON (Note)
U2 OFF
Load L1 OFF L2 OFF L1 ON L2 OFF OFF L1
Load ON L2
PGND
PGND
PGND
Note: Output is off at (1) and (4). D MODE 1 GA+ (OUT A, A ) D MODE 2 GA- (OUT A, A ) D MODE 3 GB+ (OUT B, B ) CW/CCW GB- (OUT B, B )
15
2001-09-05
TB62209F
Maximum Ratings (Ta = 25C)
Characteristics Logic supply voltage Motor supply voltage Output current Current detect pin voltage Charge pump pin maximum voltage (CCP1 Pin) Logic input voltage Power dissipation Operating temperature Storage temperature Junction temperature (Note 2) (Note 3) (Note 4) (Note 1) Symbol VDD VM IOUT VRS VH VIN PD Topr Tstg Tj Rating 7 40 1.8 VM 4.5 V VM + 7.0 to VDD + 0.4 1.4 3.2 -40 to 85 -55 to 150 150 C C C Unit V V A/phase V V V W
Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.5 A or less per phase. The current velue maybe controled according to the ambient temperature or board conditions. Note 2: Input 7 V or less as VIN. Note 3: Measured for the IC only. (Ta = 25C) Note 4: Measured when mounted on the board. (Ta = 25C) Ta: IC ambient temperature Topr: IC ambient temperature when starting operation Tj: IC chip temperature during operation Tj (max) is controlled by TSD (thermal shut down circuit)
Recommended Operating Conditions (Ta = 0 to 85C, (Note 5))
Characteristics Power supply voltage Motor supply voltage Output current Logic input voltage Clock frequency Chopping frequency Reference voltage Current detect pin voltage Symbol VDD VM IOUT (1) VIN fCLK fchop Vref VRS VDD = 5.0 V VDD = 5.0 V VM = 24 V, Torque = 100% VDD = 5.0 V Test Condition VDD = 5.0 V, Ccp1 = 0.22 F, Ccp2 = 0.02 F Ta = 25C, per phase Min 4.5 20 GND 50 2.0 0 Typ. 5.0 24 1.2 1.0 100 3.0 1.0 Max 5.5 34 1.5 VDD 150 150 VDD 4.5 Unit V V A V KHz KHz V V
Note 5: Because the maximum value of Tj is 120C, recommended maximum current usage is below 120C.
16
2001-09-05
TB62209F
Electrical Characteristics 1 (unless otherwise specified, Ta = 25C, VDD = 5 V, VM = 24 V)
Characteristics HIGH Input voltage LOW Input hysteresis voltage VIN (L) VIN (HIS) IIN (H) Input current 1 IIN (H) IIN (L) IDD1 Power dissipation (VDD Pin) IDD2 VDD = 5 V (STROBE, RESET , DATA = L), RESET = L, Logic, output all off Output OPEN, fCLK = 1.0 kHz LOGIC ACTIVE, VDD = 5 V, Charge Pump = charged Output OPEN (STROBE, RESET , DATA = L), RESET = L, Logic, output all off, Charge Pump = no operation Output OPEN, fCLK = 1 kHz LOGIC ACTIVE, VDD = 5 V, VM = 24 V, Output off, Charge Pump = charged Output OPEN, fCLK = 4 kHz LOGIC ACTIVE, 100 kHz chopping (emulation), Output OPEN, Charge Pump = charged VRS = VM = 24 V, VOUT = 0 V, STANDBY = H, RESET = L CLK = L VOUT = 0 V, STANDBY = H, RESET = L, CLK = L VRS = VM = CcpA = VOUT = 24 V, LOGIC IN = ALL = L Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (H) = 100% set Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (MH) = 85% set Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (ML) = 70% set Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (L) = 50% set Differences between output current channels IOUT = 1000 mA VRS = 24 V, VM = 24 V RESET = L (RESET state) IOUT = 1.0 A, VDD = 5.0 V Tj = 25C, Drain-Source IOUT = 1.0 A, VDD = 5.0 V Tj = 25C, Source-Drain IOUT = 1.0 A, VDD = 5.0 V Tj = 105C, Drain-Source IOUT = 1.0 A, VDD = 5.0 V Tj = 105C, Source-Drain Data input pins Data input pins with resistor Data input pins without resistor Symbol VIN (H) Data input pins GND - 0.4 200 35 1.0 GND 400 50 2.0 Test Circuit Test Condition Min 2.0 Typ. VDD Max VDD + 0.4 0.8 700 1.0 75 1.0 3.0 mA 1.0 2.5 3.5 A mV Unit
V
IM1
1.0
2.0
3.0
Power dissipation (VM Pin)
IM2
2.0
4.0
5.0
mA
IM3
10
13
Output standby current Output bias current Output leakage current
Upper
IOH
-200 -100
-150 -50 1.0
1.0
A A A
Upper Lower HIGH (Reference)
IOB IOL
VRS (H)
100
Comparator reference voltage ratio
MID HIGH MID LOW LOW
VRS (MH) VRS (ML) VRS (L) IOUT1 IOUT2 IRS RON (D-S) 1 RON (D-S) 1
83 68 48 -5 -5
85 70 50 1 0.5 0.5 0.6 0.6
87 % 72 52 5 5 2 0.6 0.6 0.75 0.75 % % A
Output current differential Output current setting differential RS pin current
Output transistor drain-source ON-resistance
RON (D-S) 2 RON (D-S) 2
17
2001-09-05
TB62209F
Electrical Characteristics 2 (Ta = 25C, VDD = 5 V, VM = 24 V, IOUT = 1.0 A)
Characteristics Symbol Test Circuit Test Condition A = 90 (16) A = 84 (15) A = 79 (14) A = 73 (13) A = 68 (12) A = 62 (11) A = 56 (10) A = 51 (9) Chopper current Vector A = 45 (8) A = 40 (7) A = 34 (6) A = 28 (5) A = 23 (4) A = 17 (3) A = 11 (2) A = 6 (1) A = 0 (0) Min 93 91 87 83 78 72 66 58 51 42 33 24 15 5 Typ. 100 100 98 96 92 88 83 77 71 63 56 47 38 29 20 10 0 Max 97 93 88 82 76 68 61 52 43 34 25 15 % Unit
18
2001-09-05
TB62209F
Electrical Characteristics 3 (unless otherwise specified, Ta = 25C, VDD = 5 V, VM = 24 V)
Characteristics Symbol Test Circuit 9 Test Condition VM = 24 V, VDD = 5 V, STANDBY = H, RESET = L, Output on, CLK = 1 kHz STANDBY = H, RESET = L, Output off, VM = 24 V, VDD = 5 V, Vref = 3.0 V VM = 24 V, VDD = 5 V, STANDBY = H, RESET = L, Output on, Vref = 2.0 to VDD - 1.0 V VDD = 5 V, VM = 24 V TjTSD = 130 to 170C VM = 24 V, STANDBY = H VDD = 5 V, STANDBY = H VDD = 5 V, VM = 24 V VDD = 5 V, TSD = operating condition VDD = 5 V, electrical angle = 0 (IB = 100%, IA = 0%) Vprotect (H) High temperature monitor pin output voltage Vprotect (L) 12 VDD = 5 V, TSD = operating condition VDD = 5 V, TSD = not operating condition VDD = 5 V, electrical angle = except 0 (IB = 100%, IA = Except 0% set) VDD = 5 V, electrical angle = 0 (IB = 100%, IA = 0%) V Min Typ. Max Unit
Vref input voltage
Vref
2.0
VDD
V
Vref input current
Iref
9
20
35
50
A
Vref attenuation ratio
Vref (GAIN)
10 11 12
1/4.8
1/5.0 TjTSD - 35 3.0 3.5 3.0 3.0
1/5.2
TSD temperature
(Note 1)
TjTSD TjTSD VDDR VMR ISD Iprotect
130 TjTSD - 50 2.0 2.0 1.0
170 TjTSD - 20 4.0 5.0 5.0
C C V V A mA
TSD return temperature difference (Note 1) VDD return voltage VM return voltage Over current protected circuit operation current (Note 2) High temperature monitor pin output current Electrical angle monitor pin output current
IMO
12
1.0
3.0
5.0
mA
VMO2 (H) Electrical angle monitor pin output voltage VMO2 (L)
12
V

Note 1: Thermal shut down (TSD) circuit When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal reset circuit is activated switching the outputs of both motors to off. When the temperature is set between 130 (min) to 170C (max), the TSD circuit operates. When the TSD circuit is activated, the charge pump is halted, and TROTECT pin outputs VDD voltage. Even if the TSD circuit is activated and Standby goes H L H instantaneously, the IC is not reset until the IC junction temperature drops -20C (typ.) below the TSD operating temperature (hysteresis function). Note 2: Overcurrent protection circuit When current exceeding the specified value flows to the output, the internal reset circuit is activated, and the ISD turns off the output. Until the Standby signal goes Low to High, the overcurrent protection circuit remains activated. During ISD, IC turns Standby mode and the charge pump halts.
19
2001-09-05
TB62209F
AC Characteristics (Ta = 25C, VM = 24 V, VDD = 5 V, 6.8 mH/5.7 )
Characteristics Clock frequency Symbol fCLK tw (tCLK) Minimum clock pulse width twp twn tr tf Output transistor switching characteristic tpLH tpHL tpLH tpHL tr Transistor switching characteristics (MO, PROTECT) tf tpLH tpHL Noise rejection dead band time CR reference signal oscillation frequency tBRANK fCR Test Circuit IOUT = 1.0 A Cosc = 560 pF, Rosc = 3.6 k VM = 24 V, VDD = 5 V, Output ACTIVE (IOUT = 1.0 A) Step fixed, Ccp1 = 0.22 F, Ccp2 = 0.01 F Output ACTIVE (IOUT = 1.0 A), CR CLK = 800 kHz Ccp = 0.22 F, Ccp = 0.01 F VM = 24 V, VDD = 5 V, STANDBY = ON OFF CLK to OUT Output Load: 6.8 mH/5.7 CR to OUT Output Load: 6.8 mH/5.7 Test Condition Output Load: 6.8 mH/5.7 Min 100 50 50 200 Typ. 100 100 1000 2000 500 1000 20 20 20 20 300 800 Max 120 400 ns kHz ns ns s Unit kHz
Chopping frequency range
fchop (min) fchop (max)
40
100
150
kHz
Chopping frequency
fchop

100
kHz s
Charge pump rise time
tONG
100
200
20
2001-09-05
TB62209F
1. Current Waveform and Setting of Mixed Decay Mode
At constant current control, in current amplitude (pulsating current) Decay mode, a point from 0 to 3 can be set using 2-bit parallel data. NF is the point where the output current reaches the set current value. RNF is the timing for monitoring the set current. The smaller the MDT value, the smaller the current ripple (peak current value). Note that current decay capability deteriorates.
fchop CR pin internal CLK waveform DECAY MODE 0 NF 12.5% MIXED DECAY MODE Charge mode NF: set current value reached Slow mode Mixed decay timing Fast mode current monitored (when set current value > output current) Charge mode
Set current value
MDT
RNF
DECAY MODE 1 NF 37.5% MIXED DECAY MODE
Set current value
MDT Charge mode NF: set current value reached Slow mode Mixed decay timing Fast mode current monitored (when set current value > output current) Charge mode
RNF
DECAY MODE 2 NF 75% MIXED DECAY MODE
Set current value
MDT Charge mode NF: set current value reached Slow mode Mixed decay timing Fast mode current monitored (when set current value > output current) Charge mode RNF
DECAY MODE 3 FAST DECAY MODE Set current value
Fast mode RNF: current monitored (when set current value > output current) Charge mode Fast mode 100% 75% 50% 25% 0
RNF
21
2001-09-05
TB62209F
2. CURRENT MODES (MIXED (SLOW + FAST) DECAY MODE Effect)
* Current value in increasing (Sine wave)
Slow Set current value Fast Slow Set current value Slow Charge Slow
Charge
Fast
Charge
Fast
Charge
Fast
Sine wave in decreasing (When using MIXED DECAY Mode with large attenuation ratio (MDT%) at attenuation)
Slow Set current value Slow Charge Charge Because current attenuates so quickly, the current immediately follows the set current value. Fast
Fast Slow Set current value Slow
Fast
Charge
Fast
*
Sine wave in decreasing (When using MIXED DECAY Mode with small attenuation ratio (MDT%) at attenuation)
Because current attenuates slowly, it takes a long time for the current to follow the set current value (or the current does not follow).
Slow Set current value Charge Fast
Slow Fast
Charge
Charge Fast Set current value Charge Fast
If RNF, current watching point, was the set current value (output current) in the mixed decay mode and in the fast decay mode, there is no charge mode but the slow + fast mode (slow to fast is at MDT) in the next chopping cycle. Note: The above charts are schematics. The actual current transient responses are curves.
22
2001-09-05
TB62209F
3. MIXED DECAY MODE waveform (Current Waveform)
fchop Internal CR CLK signal
fchop
IOUT Set current value Set current value 25% MIXED DECAY MODE NF NF
RNF MDT (MIXED DECAY TIMING) point
*
When NF is after MIXED DECAY TIMING
Fast Decay mode after Charge mode fchop fchop Set current value NF MDT (MIXED DECAY TIMING) point
IOUT
Set current value 25% MIXED DECAY MODE
NF
NF
RNF
CLK signal input
*
In MIXED DECAY MODE, when the output current > the set current value
fchop fchop fchop
Set current value IOUT
NF
Because the set current value is the output current, no CHARGE MODE in the next cycle. (Charge cancel function) RNF Set current value NF
25% MIXED DECAY MODE
RNF
MDT (MIXED DECAY TIMING) point
CLK signal input
23
2001-09-05
TB62209F
4. FAST DECAY MODE waveform
fchop Set current value IOUT
FAST DECAY MODE (100% MIXED DECAY MODE)
Because the set current value is the output current, FAST DECAY MODE in the next cycle. (Charge cancel function) RNF Set current value NF
RNF Because the set current value is the output current, CHARGE MODE NF FAST DECAY MODE in the next cycle. RNF
CLK signal input
The output current to the motor is in supply voltage mode after the current value set by Vref, RRS, or Torque reached at the set current value.
24
2001-09-05
TB62209F
5. CLK SIGNAL, INTERNAL CR CLK, AND OUTPUT CURRENT waveform (When CLK signal is input in SLOW DECAY MODE)
12.5 MIXED DECAY MODE fchop fchop Internal CR CLK signal Set current value NF MDT fchop
NF Set current value IOUT RNF MDT
RNF
CLK signal input Reset CR-CLK counter here
Momentarily enters CHARGE MODE
When CLK signal is input, the chopping counter (CR-CLK counter) is forced to reset at the next CR-CLK timing. Because of this, compared with a method in which the counter is not reset, response to the input data is faster. The delay time, the theoretical value in the logic portion, is expected to be a one-cycle CR waveform: 5 s at 100 kHz CHOPPING. When the CR counter is reset due to CLK signal input, CHARGE MODE is entered momentarily due to current comparison. Note: In FAST DECAY MODE, too, CHARGE MODE is entered momentarily due to current comparison.
25
2001-09-05
TB62209F
6. STROBE SIGNAL, INTERNAL CR CLK, AND OUTPUT CURRENT waveform (When CLK signal is input in CHARGE MODE)
12.5 MIXED DECAY MODE fchop
fchop fchop Internal CR CLK signal
Set current value
MDT
NF Set current value MDT
IOUT RNF
RNF
CLK signal input Reset CR-CLK counter here
Momentarily enters CHARGE MODE
26
2001-09-05
TB62209F
7. STROBE SIGNAL, INTERNAL CR CLK, AND OUTPUT CURRENT waveform (When STROBE signal is input in FAST DECAY MODE)
12.5
MIXED DECAY MODE fchop
fchop fchop Internal CR CLK signal Set current value IOUT NF MDT
Set current value MDT NF MDT
RNF RNF
STROBE signal input Reset CR-CLK counter here
Momentarily enters CHARGE MODE
27
2001-09-05
TB62209F
8. CLK SIGNAL, INTERNAL CR CLK, AND OUTPUT CURRENT waveform (When CLK signal is input in 2 EXCITATION MODE)
12.5 MIXED DECAY MODE fchop
fchop fchop
Set current value IOUT
0
RNF RNF MDT Set current value NF CLK signal input Reset CR-CLK counter here NF
28
2001-09-05
TB62209F
Current Discharge Path when ENABLE Input During Operation
In Slow Mode, when all output transistors are forced to switch off, coil energy is discharged in the following MODES: Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow to the parasitic diodes.
VM RRS RS pin U1 ON (Note) U2 OFF U1 OFF (Note) RRS RS pin U2 OFF U1 OFF (Note) VM VM power supply RRS RS pin U2 OFF
Load OFF L1 ON L2 ON L1
Load
Input ENABLE L2 ON L1 OFF
Load L2 OFF
PGND Charge mode
PGND Slow mode
PGND Forced OFF mode
As shown in the figure at right, an output transistor has parasitic diodes. To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to that in normal operation. As a result, the parasitic diodes are not used. If all the output transistors are forced to switch off, the energy of the coil is discharged via the parasitic diodes.
29
2001-09-05
TB62209F
Output Transistor Operating Mode
VM RRS RS pin U1 ON (Note) U2 OFF U1 OFF (Note) RRS RS pin U2 OFF U1 OFF (Note) VM VM RRS RS pin U2 ON
Load L1 OFF L2 ON L1 ON
Load L2 ON L1 ON
Load L2 OFF
PGND Charge mode
PGND Slow mode
PGND Fast mode
Output Transistor Operation Functions
CLK CHARGE SLOW FAST U1 ON OFF OFF U2 OFF OFF ON L1 OFF ON ON L2 ON ON OFF
Note: The above table is an example where current flows in the direction of the arrows in the above figures. When the current flows in the opposite direction of the arrows, see the table below.
CLK CHARGE SLOW FAST
U1 OFF OFF ON
U2 ON OFF OFF
L1 ON ON OFF
L2 OFF ON ON
30
2001-09-05
TB62209F
Power Supply Sequence (Recommended)
VDD (max) VDD (min) VDD VDDR
GND VM VM (min) VM VMR GND NON-RESET Internal reset RESET
STANDBY INPUT (Note 1)
H
STANDBY
L Takes up to tONG until operable.
Non-operable area
Note 1: If the VDD drops to the level of the VDDR or below while the specified voltage is input to the VM pin, the IC is internally reset. This is a protective measure against malfunction. Likewise, if the VM drops to the level of the VMR or below while regulation voltage is input to the VDD, the IC is internally reset as a protective measure against malfunction. To avoid malfunction, when turning on VM or VDD, to input the Standby signal at the above timing is recommended. It takes time for the output control charge pump circuit to stabilize. Wait up to tONG time after power on before driving the motors. Note 2: When the VM value is between 3.3 to 5.5 V, the internal reset is released, thus output may be on. In such a case, the charge pump cannot drive stably because of insufficient voltage. The Standby state should be maintained until VM reaches 13 V or more. Note 3: Since VDD = 0 V and VM = voltage within the rating are applied, output is turned off by internal reset. At that time, a current of several mA flows due to the Pass between VM and VDD. When voltage increases on VDD output, make sure that specified voltage is input.
31
2001-09-05
TB62209F
How to Calculate Set Current
This IC controls constant current in CLK-IN mode. At that time, the maximum current value (set current value) can be determined by setting the sensing resistor (RRS) and reference voltage (Vref). IOUT (max) = 1 Torque (Torque = 100, 85, 70, 50%) x Vref (V) x x 100 5.0 R RS ( )
1/5.0 is Vref (gain): Vref attenuation ratio. (For the specifications, see the electrical characteristics.) For example, when inputting Vref = 3 V and torque = 100% to output IOUT = 0.8 A, RRS = 0.75 (0.5 W or more) is required.
How to Calculate the Chopping and OSC Frequencies
At constant current control, this IC chops frequency using the oscillation waveform (saw tooth waveform) determined by external capacitor and resistor as a reference. The TB62209F requires an oscillation frequency of eight times the chopping frequency. The oscillation frequency is calculated as follows:
fCR = 1 0.523 x (C x R + 600 x C)
For example, when Cosc = 560 pF and Rosc = 3.6 k are connected, fCR = 813 kHz. At this time, the chopping frequency fchop is calculated as follows: fchop = fCR/8 = 101 kHz When determining the chopping frequency, make the setting taking the above into consideration.
IC Power Dissipation
IC power dissipation is classified into two: power consumed by transistors in the output block and power consumed by the logic block and the charge pump circuit. * Power consumed by the Power Transistor (calculated with RON = 0.60 ) In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower transistors of the H bridges. The following expression expresses the power consumed by the transistors of a H bridge. P (out) = 2 (Tr) x IOUT (A) x VDS (V) = 2 x IOUT2 x RON .............................. (1) The average power dissipation for output under 4-bit micro step operation (phase difference between phases A and B is 90) is determined by expression (1). Thus, power dissipation for output per unit is determined as follows (2) under the conditions below. RON = 0.60 (at 1.0 A) IOUT (Peak: max) = 1.0 A VM = 24 V VDD = 5 V P (out) = 2 (Tr) x 1.02 (A) x 0.60 () = 1.20 (W).............................................. (2) Power consumed by the logic block and IM The following standard values are used as power dissipation of the logic block and IM at operation. I (LOGIC) = 4.0 mA (typ.): I (IM3) = 15.0 mA (typ.): operation/unit I (IM1) = 4.0 mA (typ.): stop/unit The logic block is connected to VDD (5 V). IM (total of current consumed by the circuits connected to VM and current consumed by output switching) is connected to VM (24 V). Power dissipation is calculated as follows: P (Logic&IM) = 5 (V) x 0.004 (A) + 24 (V) x 0.015 (A) = 0.38 (W)................. (3) Thus, the total power dissipation (P) is P = P (out) + P (Logic&IM) = 1.51 (W) Power dissipation at standby is determined as follows: P (standby) + P (out) = 24 (V) x 0.004 (A) + 5 (V) x 0.004 (A) = 0.116 (W) For thermal design on the board, evaluate by mounting the IC.
32
2001-09-05
TB62209F
Test Waveforms
tCK CK
tCK
tpLH VM 90% tpHL 50% 50% 90%
10% GND tr tf
10%
Figure 1
Timing Waveforms and Names
33
2001-09-05
TB62209F
OSC-Charge Delay H OSC-Fast Delay
OSC (CR)
L tchop H OUTPUT Voltage A L H OUTPUT Voltage A L Set current 50% 50% 50%
OUTPUT Current
L Charge Slow Fast
OSC-charge delay: Because the rising edge level of the OSC waveform is used for converting the OSC waveform to the internal CR CLK, a delay of up to 1.25 ns (@fchop = 100 kHz: fCR = 400 kHz) occurs between the OSC waveform and the internal CR CLK.
CR-CR CLK delay
CR Waveform
Internal CR CLK Waveform
Figure 2
Timing Waveforms and Names (CR and output)
34
2001-09-05
TB62209F
Relationship between Drive Mode Input Timing and MO
CLK Waveform
MO Waveform
*
If drive mode input changes before MO timing
Drive Mode Input Waveform (1)
Drive Mode Input Internal Reflection (1)
Parallel set signal is reflected.
*
If drive mode input changes after MO timing
Drive Mode Input Waveform (2)
Drive Mode Input Internal Reflection (2)
Parallel set signal occurs after the rising edge of CLK, therefore, it is not reflected. The drive mode is changed when the electrical angle becomes 0. Note: The TB62209F uses the drive mode change reserve method to prevent the motor from step out when changing drive modes. Note that the following rules apply when switching drive modes at or near the MO signal output timing.
35
2001-09-05
TB62209F
Reflecting Points of Signals
Point where Drive Mode Setting Reflected 2-Phase Excitation mode CW/CCW
45 (MO) At rising edge of CLK input Before half-clock of phase B = phase A = 100%
1-2 Phase Excitation mode 0 (MO) At rising edge of CLK input W1-2 Phase Excitation Before half-clock of phase mode B = 100% 2W1-2 Phase Excitation mode 4W1-2 Phase Excitation mode
Other parallel set signals can be changed at any time (they are reflected immediately).
Recommended Point for Switching Drive Mode
CLK Waveform
MO Waveform
Drive mode reflected When Drive Mode Data Switching can be Input
During MO output (phase data halted) to forcibly switch drive modes, a function to set RESET = Low and to initialize the electrical angle is required.
36
2001-09-05
TB62209F
PD - Ta (Package power dissipation)
PD - Ta
3.5 3 (2)
(W) Power dissipation PD
2.5
2 1.5 (1)
1 0.5
0 0
25
50
75
100
125
150
Ambient temperature Ta (C)
(1) (2)
HSOP36 Rth (j-a) only (96C/W) When mounted on the board (140 mm x 70 mm x 1.6 mm: 38C/W: typ.)
Note: Rth (j-a): 8.5C/W
37
2001-09-05
TB62209F
Relationship between VM and VH (charge pump voltage)
VM - VH (&Vcharge UP)
50
VH voltage
charge up voltage
VM voltage
40 Charge pump voltage
Input STANDBY
(V) VH voltage, charge up voltage
30
VM voltage VMR
20 Maximum rating
10
Usable area
Recommended operation area
0 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Supply voltage VM (V) Charge pump voltage VH = VDD + VM (= Ccp A) (V)
Note: VDD = 5 V Ccp 1 = 0.22 F, Ccp 2 = 0.022 F, fchop = 150 kHz (Be aware the temperature charges of charge pump capacitor.)
38
2001-09-05
TB62209F
Operation of Charge Pump Circuit
RRS VDD = 5 V RS VM
VM = 24 V
VH
Ccp A
7
i2 Output Comparator & Controller Output H switch Tr1 Di2 Di1 (1) Vz Di3 R1 (2) i1 (2) Tr2 Ccp B Ccp 2 0.01 F Ccp 1 0.22 F
Ccp C
VH = VM + VDD = charge pump voltage i1 = charge pump current i2 = gate block power dissipation * Initial charging When RESET is released, Tr1 is turned ON and Tr2 turned OFF. Ccp 2 is charged from Ccp 2 via Di1. (2) Tr1 is turned OFF, Tr2 is turned ON, and Ccp 1 is charged from Ccp 2 via Di2. (3) When the voltage difference between VM and VH (Ccp A pin voltage = charge pump voltage) reaches VDD or higher, operation halts (Steady state). Actual operation (1) (4) (5) Ccp 1 charge is used at fchop switching and the VH potential drops. Charges up by (1) and (2) above.
*
Output switching Initial charging Steady state
VH VM
(1)
(2)
(3) t
(4)
(5)
(4)
(5)
39
2001-09-05
TB62209F
Charge Pump Rise Time
VDD + VM VM + (VDD x 90%)
Ccp 1 voltage
VM
5V STANDBY 0V tONG 50%
tONG:
Time taken for capacitor Ccp 2 (charging capacitor) to fill up Ccp 1 (storing capacitor) to VM + VDD after a reset is released. The internal IC cannot drive the gates correctly until the voltage of Ccp 1 reaches VM + VDD. Be sure to wait for tONG or longer before driving the motors. Basically, the larger the Ccp 1 capacitance, the smaller the voltage fluctuation, though the initial charge up time is longer. The smaller the Ccp 1 capacitance, the shorter the initial charge-up time but the voltage fluctuation is larger. Depending on the combination of capacitors (especially with small capacitance), voltage may not be sufficiently boosted. When the voltage does not increase sufficiently, output DMOS RON turns lower than the normal, and it raises the temperature. Thus, use the capacitors under the capacitor combination conditions (Ccp 1 = 0.22 F, Ccp 2 = 0.02 F) recommended by Toshiba.
40
2001-09-05
TB62209F
External Capacitor for Charge Pump
When driving the stepping motor with VDD = 5 V, fchop = 150 kHz, L = 10 mH under the conditions of VM = 13 V and 1.5 A, the logical values for Ccp 1 and Ccp 2 are as shown in the graph below:
Ccp 1 - Ccp 2
0.05 Applicable range 0.045 0.04
(F) Ccp 2 capacitance
0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Recommended value
Ccp 1 capacitance
(F)
Choose Ccp 1 and Ccp 2 to be combined from the above applicable range. We recommend Ccp 1:Ccp 2 at 10:1 or more. (If our recommended values (Ccp = 0.22 F, Ccp 2 = 0.02 F) are used, the drive conditions in the specification sheet are satisfied. (There is no capacitor temperature characteristic as a condition.) When setting the constants, make sure that the charge pump voltage is not below the specified value and set the constants with a margin (the larger Ccp 1 and Ccp 2, the more the margin). Some capacitors exhibit a large change in capacitance according to the temperature. Make sure the above capacitance is obtained under the usage environment temperature.
41
2001-09-05
TB62209F
(1) Low Power Dissipation mode Low Power Dissipation mode turns off phases A and B, and also halts the charge pump. Operation is the same as that when the STANDBY pin is set to Low. Motor Lock mode Motor Lock mode turns phase B output only off with phase A off. From reset, with IA = 0 and IB = 100%, the normal 4W1-2 phase operating current is output. Use this mode when you want to hold (lock) the rotor at any desired value. 2-Phase Excitation mode
100 [%] Phase B
(2)
(3)
0
Phase A
-100 STEP
2-Phase Excitation Mode
100
(typ.A)
IA
(%)
0 100
IB
(%)
Electrical angle 360 = 4 CLKs Note: 2-phase excitation has a large load change due to motor induced electromotive force. If a mode in which the current attenuation capability (current control capability) is small is used, current increase due to induced electromotive force may not be suppressed. In such a case, use a mode in which the mixed decay ratio is large. We recommend 37.5% Mixed Decay mode as the initial value (general condition).
42
2001-09-05
TB62209F
(4) 1-2 Phase Excitation mode (a)
MO CLK 100 [%]
Phase B
Phase A
0
-100
STEP
1-2 Phase Excitation Mode (typ.A)
100
IA
(%)
0
100
IB
(%)
Electrical angle 360 = 8 CLKs
43
2001-09-05
TB62209F
(5)
MO CLK 100 [%] 71
1-2 Phase Excitation mode (b)
Phase A Phase B
0
-71
-100
STEP
1-2 Phase Excitation Mode (typ.B)
100
71
IA
(%)
0
71
100
IB
(%)
Electrical angle 360 = 8 CLKs
44
2001-09-05
TB62209F
(6) W1-2 Phase Excitation mode
[%] 100 92 71
38 Phase A Phase B
0
-38
-71 -92 -100
STEP
W1-2 Phase Excitation Mode (2-bit micro step)
100 92
71
IA
(%)
38
0
38
71
92 100
IB
(%)
Electrical angle 360 = 16 CLKs
45
2001-09-05
TB62209F
(7) 2W1-2 Phase Excitation mode
[%] 100 96 88 71 Phase A 56 38
20
0
-20 Phase B -38 -56 -71 -83 -92 -98 -100
STEP
2W 1-2 Phase Excitation Mode (3-bit micro step)
100 98 92 83 71 56
IA
(%)
38
20
0
20
38
56
71
83 92 98 100
IB
(%)
Electrical angle 360 = 32 CLKs
46
2001-09-05
TB62209F
(8) 4W1-2 Phase Excitation mode
[%] 100 98 96 92 88 83 77 71 63 56 47 38 Phase A 29 20 Phase B 10
0
-10 -20 -29 -38 -47 -56 -63 -71 -77 -83 -88 -92 -96 -98 -100
STEP
Electrical angle 360 = 64 CLKs
47
2001-09-05
TB62209F
4-Bit Micro Step Output Current Vector Locus (Normalizing each step to 90)
100 98 96 92 88 83
X = 16
X = 15
X = 14 X = 13 X = 12 X = 11 X = 10 X=9 CW
77
71 CCW 63
X=8 X=7
X=6 56
(%)
47
X=5
IA
38
X=4
29
X=3
20
X=2
X 10 X X=0 0 10 20 29 38 47 56 63 71 77 83 88 92 96 98 100 X=1
IB
(%)
For input data, see the current function examples.
48
2001-09-05
TB62209F
Recommended Application Circuit
The values for the devices are all recommended values. For values under each input condition, see the above-mentioned recommended operating conditions.
Rosc = 3.6 k CR Cosc = 560 pF VDD 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V DATA MODE CLK ENABLE CW/CCW
RESET
Vref AB Vref AB 3V SGND VM RRS A A A B B RRS B RRS A 0.66 1 F
M STEPPING
MOTER 0.66
RRS B
P-GND PGND 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V DMODE 1 DMODE 2 DMODE 3 MDT 1 MDT 2 TORQUE 2 STANDBY DATA MODE Ccp A Ccp B Ccp C 5V 0V VSS (FIN) SGND PROTECT MO OPEN OPEN 5V 0V 5V 0V
TORQUE 1
5V SGND
10 F
Ccp 1 Ccp 2 0.22 F 0.01 F SGND
24 V 100 F SGND
Note: Adding bypass capacitors is recommended. Make sure that GND wiring has only one contact point, and to design the pattern that allows the heat radiation. To control setting pins in each mode by SW, make sure to pull down or pull up them to avoid high impedance. To input the data, see the section on the recommended input data. Because there may be shorts between outputs, shorts to supply, or shorts to ground, be careful when designing output lines, VDD (VM) lines, and GND lines.
49
2001-09-05
TB62209F
Package Dimensions
HSOP36-P-450-0.65
Unit: mm
Weight:
g (typ.)
50
2001-09-05
TB62209F
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
51
2001-09-05

▲Up To Search▲

Price & Availability of TB62209F

	To Download TB62209F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .